1. Field of the Invention
The present invention relates to a circuit arrangement for reshaping a pulse edge data signal whose pulse edges signal binary values of data, into an amplitude data signal whose amplitudes signal the binary values of the data, and more particularly to a reshaping arrangement which can be used within a data transmission system for decoding a signal at the receiving end and in which a pulse generator is provided which produces a timing signal whose period duration is equal to the duration of the individual binary values.
2. Summary of the Invention
The object of the present invention is to provide a circuit arrangement for reshaping a pulse edge data signal into an amplitude data signal which is independent of the speed of the items of data to be transmitted.
According to the invention, a pulse shaper is provided which, at its input, is supplied with a pulse edge data signal and which, via its output, emits a rectangular signal whose rectangular pulses are short duration and coincide with the pulse edges of the pulse edge data signal. A first bistable trigger stage and a second bistable trigger stage are provided, each of which has a setting input, a data input, a pulse train input and an output. By way of the outputs of the two trigger stages signals are emitted whose binary values signal the two stable states of the circuits. The setting input of the first trigger stage is supplied with the rectangular signal. The timing signal input of the first trigger stage is supplied with the timing signal and the first trigger stage assumes one of its two stable states when a rectangular pulse of the rectangular signal occurs. The first trigger stage assumes the other of its two stable states when, in the absence of rectangular pulses of the rectangular signal, a pulse edge of the timing signal is present at the pulse train input of the first trigger stage. The output of the first trigger stage is connected to the data input of the second trigger stage, and the pulse train input of the second trigger stage is supplied with the timing signal. The second trigger stage assumes the states of the first trigger stage when one of the edges of the timing signal occurs and the amplitude data signal is emitted by way of the output of the second trigger stage.
A circuit arrangement constructed in accordance with the present invention is characterized in that the reshaping of the pulse edge data signal into the amplitude data signal is carried out independently of the speed of the items of data to be transmitted, because the reshaping is carried out in a purely digital fashion. The higher the speed of the items of data to be transmitted, the more rapdily, on the average, do the pulse edges of the pulse edge data signal follow one another, and the more rapidly also, on the average, do the rectangular pulses of short duration of the rectangular signal follow one another, and the higher is the speed at which the two trigger stages are operated, without the need to manually adapt the circuit arrangement to different data transmission speeds.
When the speed range of the data transmission speed is to be relatively high, it is expedient to produce a rectangular signal whose rectangular pulses have steep-gradient pulse edges and have only a short duration. A rectangular signal of this type can be produced at little expense with the aid of a differentiator element and a NOT-equivalence gate. To this end, the pulse edge data signal is fed, on the one hand, directly and, on the other hand, via the differentiator element, to, in each case, one input of the NOT equivalence gate, and via its output the steep-edged rectangular pulses of short duration are emitted.